Sigma-delta converters are widely used in audio, medical, automotive and transport, entertainment (video gaming), earth-Science (Seismic Signal Detection), and telecommunications applications. Sigma-delta converters are used to quantize an analog input signal to be converted by displacing the quantization noise to a frequency-band spaced away from the band of the signal, such as to be easily filtered out. This results in improvement of the signal-to-noise (SNR) of the digital signal.
The following references include a description on Sigma Delta ADC: “Understanding Delta Sigma Data Converters,” Shreier and Temes, by IEEE Publication, John Wiley 2005; “Design of Multi-bit Delta-Sigma A/D Converters” Y. Geerts, M. Steyaert and Willy Sansen; Kluwer Intl Series in Engineering, May 1, 2002; and “On the implementation of Input-feed forward Delta-Sigma Modulators,” Amed Gharbiya and D. A. Johns, Univ Toronto, IEEE Transactions CAS II Vol. 53 No. 6, June 2006, IEEE.
A typical second-order architecture of a sigma-delta modulator, shown in FIG. 1, has two integrators and two feedback loops that inject feedback signals into both integrators. From FIG. 1, it may be evident that both integrators have an input with a feedback signal generated by the quantizer that is thusly corrupted by quantization noise.
In the feed forward architecture of a typical sigma-delta modulator shown in FIG. 2, or of a second-order sigma-delta modulator shown in FIG. 3, the input signal to be converted Vi is directly forwarded to the quantizer. This makes the loop-filter H(z) process only the quantization-noise because the direct path into the adder upstream cancels the quantized replica of the input signal Vi on the feedback path. Therefore, for a multi-bit quantizer, the integrator's output swing is small and the power consumption is reduced in respect to the architecture of FIG. 1.
The second-order single-loop feed forward sigma-delta modulator disclosed by Silva et al. (J. Silva, U. Moon, J. Steensgaard and G. C. Temes, “Wideband low-Fig distortion delta-sigma ADC topology,” El. Letters, 7 Jun. 2001) is shown in FIG. 4. The relative transfer functions are:P=Q·(−1+z−1)·z−1;R=Q·z−2;Y=X+Q·(−1+z−1)2.
It should be noted that the useful signal X is not present in nodes P and R, thus the integrators are processing only the quantization-noise (εQ) whose maximum amplitude is about 1.5 times the least significant bit (LSB). This structure may be efficient for multi-bit quantizers, in which the LSB is particularly small.
An alternative feed forward architecture for a sigma-delta converter has been proposed by Nys et al. (O. Nys, K. Henderson, “A 19-Bit Low-Power Multi-bit Sigma-Delta ADC Based on Data Weighted Averaging,” JSSC 1997) and is shown in FIG. 5. Also in this case, the equations show that the integrators do not process the useful signal X:P=Q·(−1+z−1)·z−1;R=Q·(2+z−1)·z−1;Y=X+Q·(1−z−1)2.
The advantages of the architecture of FIG. 4 may include that there are only two input branches (which correspond to a lower load for the previous stage) and the use of a single digital-to-analog converter (DAC) for feedback. By contrast, the architecture of FIG. 5 uses three input branches and two DACs. A potentially difficult feature to implement in the last two architectures is the analog-sum just upstream to the quantizer.
An analog adder may be implemented by way of a passive switched capacitor just upstream to the quantizer, as shown in FIG. 6, (A. Rusu, et al., “A Triple-Mode Sigma-Delta Modulator for Multi-Standard Wireless Radio Receivers,” An. Integrated Circ. 2006). This approach may provide good power consumption (because a passive structure is adopted), but the numerous branches may cause a SNR reduction and may force the use of a comparator with high sensitivity. Indeed, the analog adder includes an additional load at the input of the quantizer and for this reason, the quantizer comparator has a higher sensitivity to kick-back noise.
According to an alternative approach, an active analog adder is used just upstream the quantizer (L. Picolli, et al., “A 1.0 mW, 71 dB SNDR, −1.8 dBFS Input Swing, Fourth-Order SD Interface Circuit for MEMS Microphones,” ESSCIRC2009), as shown in FIG. 7. This architecture may need an additional amplifier that makes this approach less attractive for low-power applications.